74AXP1T57GT

Dual supply configurable multiple function gate

The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation. The 74AXP1T57 can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.

This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74AXP1T57GT 74AXP1T57GTX 935305668115 SOT833-1 Order product

Features

  • Wide supply voltage range:
    • VCCI: 0.7 V to 2.75 V
    • VCCO: 1.2 V to 5.5 V
  • Low input capacitance; CI = 0.6 pF (typical)
  • Low output capacitance; CO = 1.8 pF (typical)
  • Low dynamic power consumption; CPD = 0.6 pF at VCCI = 1.2 V (typical)
  • Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)
  • Low static power consumption; ICCI = 0.5 μA (85 °C maximum)
  • Low static power consumption; ICCO = 1.8 μA (85 °C maximum)
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)
    • JESD8-11A.01 (1.4 V to 1.6 V)
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A.01 (2.3 V to 2.7 V)
    • JESD8-C (2.7 V to 3.6 V; Y output)
    • JESD12-6 (4.5 V to 5.5 V; Y output)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
    • CDM JESD22-C101E exceeds 1000 V
  • Latch-up performance exceeds 100 mA per JESD78D Class II
  • Inputs accept voltages up to 2.75 V
  • Low noise overshoot and undershoot < 10 % of VCCO
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C

Target applications

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AXP1T57GTProduction0.7 - 2.751.2 - 5.5CMOS+/- 124.8701ultra low-40~1253577.8178XSON8

Package

Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackageOutline versionReflow-/Wave solderingPacking
74AXP1T57GT74AXP1T57GTX
( 9353 056 68115 )
ActiveStandard Marking
XSON8
(SOT833-1)
SOT833-1Reel 7" Q1/T1

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AXP1T57GT74AXP1T57GTX74AXP1T57GTAlways Pb-free11
Quality and reliability disclaimer

Documentation (6)

File nameTitleTypeDate
74AXP1T57Dual supply configurable multiple function gateData sheet2017-07-14
Nexperia_document_guide_Logic_translators_201711Nexperia Logic TranslatorsBrochure2017-12-05
axp1t5774AXP1T57 IBIS modelIBIS model2016-03-01
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904AXP – Extremely low-power logic technology portfolioLeaflet2019-04-05
SOT833-1_115Standard product orientation 12NC ending 115Packing2013-04-05
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyOutline drawing2018-11-14

Support

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Models

File nameTitleTypeDate
axp1t5774AXP1T57 IBIS modelIBIS model2016-03-01

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74AXP1T57GT74AXP1T57GTX935305668115Reel 7" Q1/T1Order product

Sample

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