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74LVC1G175-Q100

Single D-type flip-flop with reset; positive-edge trigger

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant inputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V).
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G175GV-Q100Production1.65 - 5.5CMOS/LVTTL± 323.1300low-40~12523240.0146SC-74; TSOP6
74LVC1G175GW-Q100Production1.65 - 5.5CMOS/LVTTL± 323.1300low-40~12526539.1154TSSOP6

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC1G175GV-Q100
SC-74; TSOP6
(SOT457)
SOT457WAVE_BG-BD-1
Reel 7" Q3/T4, ReverseActiveV7574LVC1G175GV-Q100H
( 9353 015 06125 )
74LVC1G175GW-Q100
TSSOP6
(SOT363)
SOT363WAVE_BG-BD-1
Reel 7" Q3/T4, ReverseActiveYT74LVC1G175GW-Q100H
( 9353 015 07125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74LVC1G175GV-Q10074LVC1G175GV-Q100H74LVC1G175GV-Q100Always Pb-free19.30.52E911
74LVC1G175GW-Q10074LVC1G175GW-Q100H74LVC1G175GW-Q100Always Pb-free19.30.52E911
Quality and reliability disclaimer

Documentation (12)

File nameTitleTypeDate
74LVC1G175_Q100Single D-type flip-flop with reset; positive-edge triggerData sheet2019-10-03
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc1g17574LVC1G175 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
Nexperia_Selection_guide_2021Nexperia Selection Guide 2021Selection guide2021-01-08
SOT363plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm bodyPackage information2020-04-21
MAR_SOT363MAR_SOT363 TopmarkTop marking2013-06-03
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08
SOT457plastic, surface-mounted package (SC-74; TSOP6); 6 leadsPackage information2020-04-21
MAR_SOT457MAR_SOT457 TopmarkTop marking2013-06-03
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08

Support

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Models

File nameTitleTypeDate
lvc1g17574LVC1G175 IBIS modelIBIS model2014-10-20

Ordering, pricing & availability

Sample

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