74LVC1T45GW-Q100

Dual supply translating transceiver; 3-state

The 74LVC1T45-Q100; 74LVCH1T45-Q100 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (V_CC(A) and V_CC(B)). Both V_CC(A) and V_CC(B) can be supplied with any voltage between 1.2 V and 5.5 V. This flexibility makes the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins A and DIR are referenced to V_CC(A) and pin B is referenced to V_CC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

The devices are fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH1T45-Q100 holds unused or floating data inputs at a valid logic level.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Dual supply translating transceiver; 3-state

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Features

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
- V_CC(A): 1.2 V to 5.5 V
- V_CC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
ESD protection:
- MIL-STD-883, method 3015 Class 3A exceeds 4000 V
- HBM JESD22-A114F Class 3A exceeds 4000 V
Maximum data rates:
- 420 Mbps (3.3 V to 5.0 V translation)
- 210 Mbps (translate to 3.3 V))
- 140 Mbps (translate to 2.5 V)
- 75 Mbps (translate to 1.8 V)
- 60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
±24 mA output drive (V_CC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16 μA maximum I_CC
I_OFF circuitry provides partial Power-down mode operation

Target applications

Parametrics

Type number	Product status	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74LVC1T45GW-Q100	Production	1.2 - 5.5	1.2 - 5.5	CMOS/LVTTL	± 24	2.5	1	low	-40~125	250	69.0	186	TSSOP6

Package

Type number	Orderable part number, (Ordering code (12NC))	Status	Marking	Package	Outline version	Reflow-/Wave soldering	Packing
74LVC1T45GW-Q100	74LVC1T45GW-Q100H ( 9353 009 35125 )	Active	V5	TSSOP6 (SOT363)	SOT363		Reel 7" Q3/T4, Reverse

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	RoHS / RHF	EFR	MSL	MSL leadfree
74LVC1T45GW-Q100	74LVC1T45GW-Q100H	74LVC1T45GW-Q100		123.8	1	1

Quality and reliability disclaimer

Series

74LVC(H)1T45-Q100 - Dual supply translating transceiver; 3-state

Documentation (6)

File name	Title	Type	Date
74LVC_LVCH1T45_Q100	Dual supply translating transceiver; 3-state	Data sheet	2019-03-19
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11009	Pin FMEA for LVC family	Application note	2019-01-09
lvc1t45	lvc1t45 IBIS model	IBIS model	2013-04-07
SOT363_125	Tape reel SMD; reversed product orientation 12NC ending 125	Packing	2012-11-20
SOT363	plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm body	Outline drawing	2018-11-14

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Models

File name	Title	Type	Date
lvc1t45	lvc1t45 IBIS model	IBIS model	2013-04-07

Ordering, pricing & availability

Type number	Orderable part number	Ordering code (12NC)	Packing	Buy online
74LVC1T45GW-Q100	74LVC1T45GW-Q100H	935300935125	Reel 7" Q3/T4, Reverse	Order product

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