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74AVC4T3144-Q100

4-bit dual-supply buffer/level translator; 3-state

The 74AVC4T3144-Q100 is a 4-bit, dual-supply level translating buffer with 3-state outputs. It features four data inputs (An and B4), four data outputs (YBn and YA4), and an output enable input (OE). The device is configured to translate three inputs from VCC(A) to VCC(B) and one input from VCC(B) to VCC(A). OE, An and YA4 are referenced to VCC(A) and YBn and B4 are referenced to VCC(B). A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables outputs, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all outputs are in the high-impedance OFF-state.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range:

    • VCC(A): 0.8 V to 3.6 V

    • VCC(B): 0.8 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • MIL-STD-883, method 3015 Class 3B exceeds 8000 V

    • HBM JESD22-A114E Class 3B exceeds 8000 V

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Suspend mode

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • IOFF circuitry provides partial Power-down mode operation

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AVC4T3144GU12-Q100Production0.8 - 3.60.8 - 3.6CMOS/LVTTL± 124.64very low-40~1251886.296XQFN12

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74AVC4T3144GU12-Q100
XQFN12
(SOT1174-1)
SOT1174-1SOT1174-1_115ActiveStandard Marking74AVC4T3144GU12-QX
( 9356 909 12115 )

Environmental information

Type numberOrderable part numberChemical contentRoHSRHF-indicatorLeadfree conversion date
74AVC4T3144GU12-Q10074AVC4T3144GU12-QX74AVC4T3144GU12-Q100
Quality and reliability disclaimer

Documentation (6)

File nameTitleTypeDate
74AVC4T3144_Q1004-bit dual-supply buffer/level translator; 3-stateData sheet2019-11-15
AN90007Pin FMEA for AVC familyApplication note2018-11-30
avc4t3144IBIS model of 74AVC4T3144IBIS model2017-12-22
74AVC4T3144_and_74LVC4T3144_leafletDual supply translating buffers/line driversLeaflet2018-03-09
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT1174-1plastic, leadless extremely thin quad flat package; 12 terminals; 0.4 mm pitch; 2 mm x 1.7 mm x 0.5 mm bodyPackage information2022-06-07

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Models

File nameTitleTypeDate
avc4t3144IBIS model of 74AVC4T3144IBIS model2017-12-22

Ordering, pricing & availability

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