74ALVT162821

2.5 V / 3.3 V 20-bit bus-interface D-type flip-flop, positive-edge trigger with 30 Ohm termination resistors; 3-state

The 74ALVT162821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V.

The 74ALVT162821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is Highthe outputs are in high impedance "off" state, which means they will neither drive nor load the bus.

The 74ALVT162821 is designed with 30 Ω series resistance in both High and Low output stages. This design reduces the line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters. The series termination resistors reduce overshoot and undershoot and are ideal for driving memory arrays.

Features and benefits

  • Outputs include series resistance of 30 Ω making external termination resistors unnecessary
  • 20-bit positive-edge triggered register
  • 5 V I/O Compatible
  • Multiple VCC and GND pins minimize switching noise
  • Live insertion/extraction permitted
  • Power-up reset
  • Power-up 3-State
  • Output capability ±12 mA
  • Latch-up protection exceeds 500 mA per Jedec Std 17
  • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
  • Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVT162821DGGProduction2.3 - 3.6TTL± 123.2150medium-40~859321.0TSSOP56

Package

Type numberPackagePackage informationReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74ALVT162821DGG
TSSOP56
(SOT364-1)
SOT364-1SSOP-TSSOP-VSO-WAVE
Tube in DrypackActiveALVT16282174ALVT162821DGGS
( 9352 554 60512 )
Reel 13" Q1/T1 in DrypackActiveALVT16282174ALVT162821DGGY
( 9352 554 60518 )

Discontinuation information

Type numberOrderable part number, (Ordering code (12NC))Last time buy dateLast time delivery dateReplacement productStatusComments
74ALVT162821DGG935255460112
74ALVT162821DGG935255460118

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRIFRMTBF (hour)MSLMSL leadfree
74ALVT162821DGG74ALVT162821DGGS74ALVT162821DGGAlways Pb-free70.81.337.52E822
74ALVT162821DGG74ALVT162821DGGY74ALVT162821DGGAlways Pb-free70.81.337.52E822
Quality and reliability disclaimer

Documentation (6)

File nameTitleTypeDate
74ALVT16282120-bit bus-interface D-type flip-flop; positive-edge trigger with 30 Ohm termination resistors; 3-stateData sheet2018-01-26
alvt162821alvt162821 IBIS modelIBIS model2013-04-07
Nexperia_Selection_guide_2020Nexperia Selection Guide 2020Selection guide2020-01-31
alvt16alvt16 Spice modelSPICE model2013-05-06
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyPackage information2020-04-21

Support

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Models

File nameTitleTypeDate
alvt162821alvt162821 IBIS modelIBIS model2013-04-07
alvt16alvt16 Spice modelSPICE model2013-05-06

Ordering, pricing & availability

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