74AUP1T34GW-Q100 PCB Symbol, Footprint & ECAD Model

Low-power dual supply translating buffer

The 74AUP1T34-Q100 provides a single buffer with two separate supply voltages. InputA is designed to track V_CC(A). OutputY is designed to track V_CC(Y). Both, V_CC(A) and V_CC(Y) accepts any supply voltage from 1.1V to 3.6V. This feature allows universal low voltage interfacing between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 1.1V to 3.6V. This device ensures a very low static and dynamic power consumption across the entire V_CC range from 1.1V to 3.6V. This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Low-power dual supply translating buffer

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*** Authorized resellers for overstock, mature, and discontinued products which are warranted for reliability by the reseller, no longer by Nexperia

Features

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40°C to +85°C and from -40°C to +125°C
Wide supply voltage range from 1.1 V to 3.6V
High noise immunity
Complies with JEDEC standards:
- JESD8-7 (1.2 V to 1.95V)
- JESD8-5 (1.8 V to 2.7V)
- JESD8-B (2.7 V to 3.6V)
ESD protection:
- MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
- HBM JESD22-A114F Class 3A. Exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V (C = 200pF, R = 0Ω)
Wide supply voltage range:
- V_CC(A): 1.1 V to 3.6 V
- V_CC(Y): 1.1 V to 3.6 V
Low static power consumption; I_CC = 0.9μA (maximum)
Each port operates over the full 1.1 V to 3.6 V power supply range
Latch-up performance exceeds 100mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OF _F circuitry provides partial Power-down mode operation

Target applications

Parametrics

Type number	Product status	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1T34GW-Q100	Production	1.1 - 3.6	1.1 - 3.6	CMOS	± 1.9	15.2	1	ultra low	-40~125	398	23.0	258	TSSOP5

Package

Type number	Orderable part number, (Ordering code (12NC))	Status	Marking	Package	Outline version	Reflow-/Wave soldering	Packing
74AUP1T34GW-Q100	74AUP1T34GW-Q100H ( 9353 020 98125 )	Active	pQ	TSSOP5 (SOT353-1)	SOT353-1		Reel 7" Q3/T4, Reverse

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	RoHS / RHF	MSL	MSL leadfree
74AUP1T34GW-Q100	74AUP1T34GW-Q100H	74AUP1T34GW-Q100		1	1

Quality and reliability disclaimer

Series

Documentation (7)

File name	Title	Type	Date
74AUP1T34_Q100	Low-power dual supply translating buffer	Data sheet	2019-01-28
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1t34	74AUP1T34 IBIS model	IBIS model	2014-12-14
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
SOT353-1_125	TSSOP5; Reel pack; SMD, 7"; Q3 Reversed product orientation; Orderable part number ending, 125 or H; Ordering code (12NC) ending 125	Packing	2017-11-16
SOT353-1	plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body	Outline drawing	2017-01-30

Support

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Models

File name	Title	Type	Date
aup1t34	74AUP1T34 IBIS model	IBIS model	2014-12-14

Ordering, pricing & availability

Type number	Orderable part number	Ordering code (12NC)	Packing	Buy online
74AUP1T34GW-Q100	74AUP1T34GW-Q100H	935302098125	Reel 7" Q3/T4, Reverse	Order product

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