74LVC1G175

Single D-type flip-flop with reset; positive-edge trigger

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Features and benefits

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V.
±24 mA output drive (V_CC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.

Parametrics

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74LVC1G175GM	Production	1.65 - 5.5	CMOS/LVTTL	± 32	3.1	300	low	-40~125	291	6.6	145	XSON6
74LVC1G175GN	Production	1.65 - 5.5	CMOS/LVTTL	± 32	3.1	300	low	-40~125	277	12.1	172	XSON6
74LVC1G175GS	Production	1.65 - 5.5	CMOS/LVTTL	± 32	3.1	300	low	-40~125	273	15.3	178	XSON6
74LVC1G175GV	Production	1.65 - 5.5	CMOS/LVTTL	± 32	3.1	300	low	-40~125	232	40.0	146	SC-74; TSOP6
74LVC1G175GW	Production	1.65 - 5.5	CMOS/LVTTL	± 32	3.1	300	low	-40~125	265	39.1	154	TSSOP6

Package

Type number	Package	Package information	Packing	Status	Marking	Orderable part number, (Ordering code (12NC))
74LVC1G175GM	XSON6 (SOT886)	SOT886	Reel 7" Q1/T1, Q3/T4	Active	YT	74LVC1G175GM,132 ( 9352 772 08132 )
74LVC1G175GM	XSON6 (SOT886)	SOT886	Reel 7” Q1/T1 or Q2/T3	Active	YT	74LVC1G175GM,115 ( 9352 772 08115 )
74LVC1G175GN	XSON6 (SOT1115)	SOT1115	Reel 7" Q1/T1, Q3/T4	Active	YT	74LVC1G175GN,132 ( 9352 917 79132 )
74LVC1G175GS	XSON6 (SOT1202)	SOT1202	Reel 7" Q1/T1, Q3/T4	Active	YT	74LVC1G175GS,132 ( 9352 929 05132 )
74LVC1G175GV	SC-74; TSOP6 (SOT457)	SOT457	Reel 7" Q3/T4, Reverse	Active	V75	74LVC1G175GV,125 ( 9352 749 47125 )
74LVC1G175GW	TSSOP6 (SOT363)	SOT363	Reel 7" Q3/T4, Reverse	Active	YT	74LVC1G175GW,125 ( 9352 749 48125 )

Discontinuation information

Type number	Orderable part number, (Ordering code (12NC))	Last time buy date	Last time delivery date	Replacement product	Status	Comments
74LVC1G175GW	935274948165

Quality, reliability & chemical content

Type number	Orderable part number	Chemical content	Leadfree conversion date	EFR	IFR	MTBF (hour)	MSL	MSL leadfree
74LVC1G175GM	74LVC1G175GM,132	74LVC1G175GM	Always Pb-free	19.6	0.7	1.63E5	1	1
74LVC1G175GM	74LVC1G175GM,115	74LVC1G175GM	Always Pb-free	19.6	0.7	1.63E5	1	1
74LVC1G175GN	74LVC1G175GN,132	74LVC1G175GN	Always Pb-free	19.6	0.7	1.63E5	1	1
74LVC1G175GS	74LVC1G175GS,132	74LVC1G175GS	Always Pb-free	19.6	0.7	1.63E5	1	1
74LVC1G175GV	74LVC1G175GV,125	74LVC1G175GV	Always Pb-free	19.6	0.7	1.63E5	1	1
74LVC1G175GW	74LVC1G175GW,125	74LVC1G175GW	Always Pb-free	19.6	0.7	1.63E5	1	1

Quality and reliability disclaimer

Documentation (16)

File name	Title	Type	Date
74LVC1G175	Single D-type flip-flop with reset; positive-edge trigger	Data sheet	2021-06-10
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11009	Pin FMEA for LVC family	Application note	2019-01-09
lvc1g175	74LVC1G175 IBIS model	IBIS model	2014-10-20
Nexperia_Selection_guide_2020	Nexperia Selection Guide 2020	Selection guide	2020-01-31
Nexperia_Selection_guide_2021	Nexperia Selection Guide 2021	Selection guide	2021-01-08
SOT1202	plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1mm x 0.35 mm body	Package information	2020-04-21
MAR_SOT1202	MAR_SOT1202 Topmark	Top marking	2013-06-03
SOT1115	plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm body	Package information	2020-04-21
MAR_SOT1115	MAR_SOT1115 Topmark	Top marking	2013-06-03
SOT363	plastic, surface-mounted package; 6 leads; 0.65 mm pitch; 2.1 mm x 1.25 mm x 0.95 mm body	Package information	2020-04-21
MAR_SOT363	MAR_SOT363 Topmark	Top marking	2013-06-03
SOT886	plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body	Package information	2020-04-21
MAR_SOT886	MAR_SOT886 Topmark	Top marking	2013-06-03
SOT457	plastic, surface-mounted package (SC-74; TSOP6); 6 leads	Package information	2020-04-21
MAR_SOT457	MAR_SOT457 Topmark	Top marking	2013-06-03

Support

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Models

File name	Title	Type	Date
lvc1g175	74LVC1G175 IBIS model	IBIS model	2014-10-20

Ordering, pricing & availability

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