74LVC2T45DC-Q100

Dual supply translating transceiver; 3-state

The 74LVC2T45-Q100; 74LVCH2T45-Q100 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two 2-bits input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied with any voltage between 1.2 V and 5.5 V. This feature makes the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH2T45-Q100 holds unused or floating data inputs at a valid logic level.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range:
    • VCC(A): 1.2 V to 5.5 V
    • VCC(B): 1.2 V to 5.5 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
    • JESD36 (4.5 V to 5.5 V)
  • ESD protection:
    • MIL-STD-883, method 3015 Class 3A exceeds 4000 V
    • HBM JESD22-A114F Class 3A exceeds 4000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • Maximum data rates:
    • 420 Mbps (3.3 V to 5.0 V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
    • 60 Mbps (translate to 1.5 V)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • ±24 mA output drive (VCC = 3.0 V)
  • Inputs accept voltages up to 5.5 V
  • Low power consumption: 16 μA maximum ICC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options

Target applications

Parametrics

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74LVC2T45DC-Q100Production1.2 - 5.51.2 - 5.5CMOS/LVTTL+/- 242.52low-40~12520651.0VSSOP8

Package

Type numberPackageOutline versionReflow-/Wave solderingPackingStatusMarkingOrderable part number, (Ordering code (12NC))
74LVC2T45DC-Q100
VSSOP8
(SOT765-1)
SOT765-1Reel 7" Q3/T4, ReverseActiveV4574LVC2T45DC-Q100H
( 9353 004 61125 )

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateEFRMSLMSL leadfree
74LVC2T45DC-Q10074LVC2T45DC-Q100H74LVC2T45DC-Q100Always Pb-free123.811
Quality and reliability disclaimer

Documentation (8)

File nameTitleTypeDate
74LVC_LVCH2T45_Q100Dual supply translating transceiver; 3-stateData sheet2018-08-13
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2011-02-04
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
75017668Low voltage CMOS family - LVCBrochure2015-07-09
lvc2t45lvc2t45 IBIS modelIBIS model2013-04-07
SOT765-1_125VSSOP8; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code (12NC) ending 125Packing2013-05-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyOutline drawing2018-10-18

Support

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Models

File nameTitleTypeDate
lvc2t45lvc2t45 IBIS modelIBIS model2013-04-07

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