74AUP1G74GN

Low-power D-type flip-flop with set and reset; positive-edge trigger

The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74AUP1G74GN 74AUP1G74GN,115 935292215115 SOT1116 Order product

Features

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Target applications

Parametrics

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G74GNProduction1.1 - 3.6CMOS+/- 1.99.2400ultra low-40~12523810.6148XSON8

Package

Type numberOrderable part number, (Ordering code (12NC))StatusMarkingPackageOutline versionReflow-/Wave solderingPacking
74AUP1G74GN74AUP1G74GN,115
( 9352 922 15115 )
Active54
XSON8
(SOT1116)
SOT1116Reel 7" Q1/T1

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHS / RHFLeadfree conversion dateMSLMSL leadfree
74AUP1G74GN74AUP1G74GN,11574AUP1G74GNAlways Pb-free11
Quality and reliability disclaimer

Documentation (6)

File nameTitleTypeDate
74AUP1G74Low-power D-type flip-flop with set and reset; positive-edge triggerData sheet2017-07-14
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g74aup1g74 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
SOT1116_115Standard product orientation 12NC ending 115Packing2013-04-04
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyOutline drawing2018-11-14

Support

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Models

File nameTitleTypeDate
aup1g74aup1g74 IBIS modelIBIS model2013-04-07

Ordering, pricing & availability

Type numberOrderable part numberOrdering code (12NC)PackingBuy online
74AUP1G74GN74AUP1G74GN,115935292215115Reel 7" Q1/T1Order product

Sample

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